|The symbols supplied with the Fermi_central_library
are our best example of how we think a symbol should be made. It is reasonable
to look at these as samples when creating your own symbols. Many people
have valid but different views on this subject and are encouraged to change
their symbols any way they think best. Those symbols will NOT, however,
be placed in the Fermi_central_library. Our focus is to provide correct
and functional parts with a consistent appearance where possible. We simply
cannot introduce many conflicting styles of symbols and also get some work
There are two ways to make a symbol - Specific and Generic.
· A generic method would be used when you are creating a device that has more than one identical gate. A 7400 AND gate is an example. The pin number properties in the symbol would be empty and would later be filled in during device place (or when packaged). The AND gate symbol is the same for each slot, only the pin numbers change. The pin numbers would then be added in the PDB in a way that allows for (or dis-allows) pin and gate swapping.
|It is also useful to have more than
one symbol included in the PDB to provide for a more readable schematic.
Examples are a NAND gate and a NOR gate for the 7400 device.
We are also adding power and ground pins to symbols because the old method of assigning these pins implicitly rarely works well. Power pins may be VCC, or they may be +3.3V.
Some details we use to create a symbol are:
All pins MUST be on a 0.10 grid.
2) Usually, the only visible property holders are the Ref Designator, pin numbers, part numbers and Value.
3) All rotations and mirrors are right reading and similarly placed to present a pleasing and functional view.
4) The text size is .120.
5) The format is changed according to its position (for example: right/center/left bottom/middle/top and rotation).
6) All rotation and mirror views are also adjusted to look as much like the composite view as possible.
| The following picture is a good example
of how to make a discrete symbol.
Another example is a connector symbol. This symbol normally appears on a connector page and would use CON_INTER_I, CON_INTER_O or CON_INTER_BI symbol to connect to a net on a different page. This is a reasonably safe way to use a connector without pins getting swapped unexpectedly.
The following picture is an example of a generic symbol that is used for more than one type of IC. The text PIN NUMBER is an empty property holder that will have the correct pin information after placement. Since the pin numbers are normally only 1 or 2 characters long, the placement of the property holder must take that into account. Sometimes that will cause the PIN NUMBER field to overlap other fields. This is acceptable in this case because the pin numbers will not use the whole pin number field.
Another OPAMP with power pins note that the power pins are offset. This is to prevent a mirrored part from connecting to the wrong power if replaced later in the design.
The next example is of a FPGA. As the parts get bigger, we are faced with how to show the pin out and also display a nice flow on the schematic. One way is to put the symbol in a hierarchical block and show the pins as they appear on the device. At the hierarchical view, inputs and outputs can be placed anywhere the designer wants them.
The last picture is an example of an IC. Notice the spacing of the pins and the body of the IC. Where possible, this is the desired look and will allow other symbols to more naturally mesh with all other symbols. If the pin names are too long, the body of the IC should be enlarged as needed. For a large IC, the shape will need to be enlarged a lot to accommodate the number of pins.
last modified 04/06/2004 Comments or Questions? EED Webmaster
|Security, Privacy, Legal|